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EE - MOS transistor theory Questions

Question # 00018249
Subject: Engineering
Due on: 06/24/2014
Posted On: 06/24/2014 07:30 AM

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MOS transistor theory
CMOS Inverters and gates
Design a CMOS function implementing Z=ABC+D+EF matching
a standard inverter.
3.1 How is capacitance estimated in deep sub-micron? What are the two
3.2 Calculate the capacitance for a given piece of layout for the HP processs.
3.3 Calculate the capacitance for a given piece of layout to several layers.
Passive devices
Draw a typical poly-poly capacitor layout. Why are fingers included?
What are sources of “Stray” capacitance in capacitors
Design a matched set of 3 capacitor with ratios 1, 2, 3. Show a
layout with all required symmetries to correct for gradients.
Why are diffusion capacitors not often used?
How close can capacitors be matched?
What are 3 common layers used to construct resistors?
Draw a layout example of two matched well resistors of 20k
ohms each.
4.8 Why are guard rings placed around well and diffusion resistors?
Why are guard rings good around capacitors?

GM related things
What value of Gm should be used to obtain an amplifier with a gain of 10 when RL
is 10k ohms?
What assumptions are made for small signal operation?
Why is layout important in Mixed signal design?
How are devices matched in Mixed signal design?
Why are device ratios used instead of device values in mixed signal design?
Why must the number of invertors in a ring oscillator be odd?
How can a ring oscillator be started and stopped? What logic elements are added?
8.1 Draw the block diagram for a PLL and explain each circuit function
8.2 Calculate output frequencies from PLL specifications and reference clock rate.
(M/N ratios)
When should an XOR PD be used?
What is Kvco, Kpd and how are they determined?
What is the natural frequency of a PLL?

Current sources and sinks and references
Draw schematics for a current mirror
Why are cascade transistors used?
Design a current reference using a single resistor
Draw the schematic diagram for a band gap voltage

10.5 How can a band gap voltage reference be used with an external resistor to
provide a precision current reference?
Design a current mirror that will provide 3X the current out vrs. Current in.
10.7 How can currents be added and subtracted?

What conditions must be met for amplifier stability?
Draw schematics for a source coupled pair amplifier.
What is CMRR (CMR) ?
What are the benefits of a current source loaded amplifier?
What is IOS?
What is PSSR?
What is slew rate?
What is an “instrumentation” amplifier? Draw schematics for a typical circuit
Non Linear mixed signal circuits
How can circuits be implemented that perform the ln, exp, square, and square root
How can ln and exp functions be used to perform multiplication?
How can square law circuits be used to perform multiplication?
What must be done to the length to ensure the transistors approach the square law
Data converters
Design a switched capacitance D/A

Design a switched capacitance A/D
Design a current mode D/A converter
What is a Thermometer code? How is it important to D/A design?
What is a pipelined A/D converter? Draw a block diagram.
Why are multiple pipelined A/D converters combined?
What voltage could a N bit converter discern if the Vdd is 2.5V, and N=10?
What is DNL?
What is INL?
What is Gain Error?
What is SNR?
What is ENOB? How is it determined?
What does monotonic increasing mean?
Why are guard rings included in D/A and A/D designs?
What is glitch energy?

I/O Buffers
Draw an ESD circuit. Explain how it works.
Why are guard rings used in I/O design. Draw the latch
up devices, and show their origin on a chip view.

Current mode analog
Draw schematics for current mode circuits that add, subtract, multiply, and divide
Draw schematics for a current mode inverter and 2 input NOR gate
Draw schematics for a current mode comparator
Why are cascade devices used in current mode circuits
Why are switched current circuits typically faster than
switched capacitor circuits
How can digital current source matching be implemented? Draw a circuit to illustrate.
Why is current mode analog interesting in future very deep submicron processes? What
fundamental limits can it help overcome?
Switched Capacitor circuits
Draw circuits for a SC resistor equivalent
What is the benefit of a SC resistor over a poly resistor
How can the resistance of a SC resistor be made larger
How can the capacitor size of a given SC resistor value be made smaller
How can a SC resistor be made to have a negative value
What switching rates are typical for a SC circuit?
What is the equation for a simple SC resistor?
How can the frequency response of a SC filter be changed without altering any physical devices?
Draw the circuit for a charge mode integrator and explain how it works
Draw the circuit for a resistive SC amplifier, and explain how it works
How can digital capacitor matching be implemented? Draw schematics of an example to
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EE - MOS transistor theory Questions Solution Paper

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Posted On: 06/24/2014 07:32 AM
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Tutorial Preview …Solution xxxxxxxxxxxxx…
EE_-_MOS_transistor_theory_Questions_Solution_Paper.docx (1070.73 KB)
Preview: below:XOR xxxxx detector xxxxxxxx curve The xxxxxxx lock point xxxx an xxx xxxxx detector xx also at xxx 90° static xxxxx shift xxxxx xxxx is xxxxx Kpd and xxx are they xxxxxxxxxxx Ans: xxxx xxxxxxx should xx low because xxx power supply xxxxxxxxxxx of xxx xxx is xxxxx Hence your xxx detereministic jitter xx lower xx xxxx But xx the other xxxxx a high xxxx will xxxx xxxx you x better loop xxxxxxxxx which eliminates xxx lower xxxxxxxxx xxxxx on xxx VCO However, xxxx respect to xxx variation xxxxx xx the xxxx KVCO range xx not safe xxxxxxx you xxxxxx xxxxxx get xxxx numbers with xxxxxxx to the xxxxxxx conditions xxxxxxx xxx temp xxxxxxx will give xxxxxxxxx high gains xxx slower, xxxx xxxx corners xxxxx give horrible xxxxx This will xxxxxx the xxxxxxxxx xx the xxx over PVT xxx is the xxxxxx current xxxx xxxx measuring xxxxxxx with the xxxxxxxx the result xx a xxxxxxx xxxx average xxxxxxx then varies xxxxxxxxx to the xxxxxxxxx of xxx xxxxxxxxx error xx measure the xxxxxxx current, ground xxxxxx the xx xx Ref xxxxx Disconnect CP xxxxxx to ammeter xxxxxxx other xxx xx ammeter xx Vp or xxxxxx depending on xxx polarity xxxx xx the xxxxxxx frequency of x PLL? Natural xxxxxxxxx of xxx xxx be xxxxxxxx as?n = xxxxxxxxxxxx sources and xxxxx and xxxxxxxxxx xxxx schematics xxx a current xxxxxx Ans A xxxxxxx mirror xx x circuit xxxxxxxx to copy x current through xxx active xxxxxx xx controlling xxx current in xxxxxxx active device xx a xxxxxxxx xxxxxxx the xxxxxx current constant xxxxxxxxxx of loading xxx current xxxxx xxxxxxxx can xxx and sometimes xxx a varying xxxxxx current xxxxxxxxxxxxx xx ideal xxxxxxx mirror is xxxxxx an ideal xxxxxxxxx current xxxxxxxxx xxxx reverses xxx current direction xx well or xx is x xxxxxxxxxxxxxxxxxx current xxxxxx (CCCS) The xxxxxxx mirror is xxxx to xxxxxxx xxxx currents xxx active loads xx circuitsWhy are xxxxxxx transistors xxxxx xxx cascode xxxxxxxx input-output isolation xxx reverse transmission) xx there xx xx direct xxxxxxxx from the xxxxxx to input xxxx eliminates xxx xxxxxx effect xxx thus contributes xx a much xxxxxx bandwidth xxxxxx x current xxxxxxxxx using a xxxxxx resistor Draw xxx schematic xxxxxxx xxx a xxxx gap voltage xxxxxxxxxxxxxxxx Voltage Reference xx 5 xxx xxx a xxxx gap voltage xxxxxxxxx be used xxxx an xxxxxxxx xxxxxxxx to xxxxxxx a precision xxxxxxx reference? Design x current xxxxxx xxxx will xxxxxxx 3X the xxxxxxx out vrs xxxxxxx in xxxxxxxx xxxxxxxx connected xxxx provide additional xxxxx gain which xxxxxxx in xxxxxxx xxxxxxxx of.....
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